1. Field of the Invention
The present invention relates to the control of power in CMOS devices. More particularly, the present invention relates to the control of a synchronized clock in a CMOS device.
2. Art Background
Many solid state components such as processors and memory devices are implemented with CMOS circuits when they are utilized for power sensitive applications. CMOS circuits are desirable for low power operation as CMOS circuits dissipate very little power when not actively clocked. This provides a natural low power state for a system. Power is simply controlled by disabling the clock.
An exemplary block diagram of a CMOS component controlled by a system clock is shown in FIG. 1. An external clock source 10 generates a system clock 20. Access by the CMOS component 30 to the clock signal 10 is controlled by the clock enable signal 40 generated by the processor or controller 50. The clock source 10 can be enabled and disabled quickly by the processor 50 to correspondingly turn off the CMOS component 30. The clock signal is buffered by clock buffer 55 in the CMOS component 30 in order to drive the capacitive load presented by the logic and memory circuits 60. In high performance CMOS devices, however, it may not be possible simply turn off the clock source. For example, when the CMOS device uses phase lock loop (PLL) or delay lock loop (DLL) circuits to create a synthesized clock, from the external clock signal received, the PLL/DLL may require long intervals of times, in the order of hundreds or thousands of clock cycles, in order to relock to the external clock. Thus, when the PLL/DLL is powered down, it becomes unsynchronized to the external clock. Therefore, each power down and power up process would require many clock cycles before the circuit was locked, synchronized and operational, making power down operations undesirable due to the latency involved.